Power management plays an important role in the current day electronics industry. Battery powered and handheld devices require power management techniques to extend battery life and improve the performance and operation of the devices. One aspect of power management includes controlling operational voltages. Conventional electronic systems, particularly systems on-chip (SOCs) commonly include various subsystems. The various subsystems may be operated under different operational voltages tailored to the specific needs of the subsystems. Voltage regulators are employed to deliver specified voltages to the various subsystems. Voltage regulators may also be employed to keep the subsystems isolated from one another.
Low dropout (LDO) voltage regulators are commonly used to generate and supply low voltages, and achieve low-noise circuitry. Conventional LDO voltage regulators require a large external capacitor, frequently in the range of a several microfarads. These external capacitors occupy valuable board space, increase the integrated circuit (IC) pin count, and prevent efficient SOC solutions.
With reference to FIG. 1, a conventional LDO voltage regulator 100 with capacitor CL is illustrated. Capacitor CL is problematic, as discussed above. As illustrated, LDO voltage regulator 100 accepts an unregulated input voltage Vin and an input reference voltage Vref, and generates a regulated output voltage Vout. One input of differential amplifier 102 monitors a fraction of regulated output voltage Vout, as determined by the resistance ratio of resistors R1 and R2. The other input to differential amplifier 102 is stable, reference voltage Vref. The output of differential amplifier 102 drives a large pass transistor, transistor 104. If regulated output voltage Vout, which is derived at the output of transistor 104 rises too high relative to reference voltage Vref, then differential amplifier 102 alters the drive strength to transistor 104 in order to maintain regulated output voltage Vout at a constant voltage value.
Conventional LDO voltage regulator 100 of FIG. 1 is a “two pole” system. A “pole,” as is well known in control systems associated with electrical circuits is an indication of stability of the electrical circuit. Specifically, with respect to resistor-capacitor circuits, a loop gain plotted over a range of frequencies of the alternating current passing through the circuit would increase dramatically at the poles of the circuit. In order to maintain stability of the circuit at these poles, the poles are compensated with other circuit elements which act as damping factors on the loop gain. If multiple poles exist, for example, due to multiple resistor-capacitor combinations, focus may be placed on compensating the dominant pole. In such systems, it is desirable that a non-dominant pole lies close to the dominant pole, such that compensation circuits may be effectively employed in stabilizing both the dominant and the non-dominant pole.
Returning to FIG. 1, a non-dominant pole is formed at the gate of transistor 104. Capacitor CL contributes to the dominant pole. In order to achieve system stability, resistor RESR is introduced as shown. However, it is extremely difficult to control RESR with sufficient precision in order to ensure stability of LDO voltage regulator 100 over both poles. Therefore, as an alternative, the size of capacitor CL is increased, sometimes to the order of several microfarads, which leads to the numerous above-described problems. Accordingly, there arises in the art for solutions which do not require a large capacitor CL for establishing stability of LDO voltage regulator 100. In other words, there is a need for capacitor-less solutions of LDO voltage regulators.
Prior efforts to eliminate the capacitor from LDO voltage regulators suffer from severe drawbacks. For example, a damping factor control (DFC) block is utilized in K. N. Leung and P. K. T. Mok, “A capacitor - free CMOS low - dropout regulator with damping - factor - control frequency compensation ”, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, October 2003 (hereinafter, “Leung”). However, the DFC block of Leung is essentially an amplifier which includes a capacitor to boost the capacitive load at the output of the error amplifier. This capacitor creates a dominant pole. As a result, the technique of Leung requires a minimum of 1 mA current-load in order to ensure stability of the LDO voltage regulator. Supporting such large current-loads, in the order of several mAs is not feasible. Thus, Leung's LDO voltage regulator is not suitable for efficient SOC implementations.
In another example, a quality factor (Q) reduction technique is proposed in S. K. Lau, P. K. T. Mok, K. N. Leung, “A low - dropout regulator for SoC with Q - reduction ”, IEEE Journal of Solid-State Circuits, Vol. 42, No.3, March 2007 (hereinafter, “Lau”). Lau's technique includes a capacitor and a diode to control the peak gain of the LDO voltage regulator. However, Lau's technique also suffers from the drawback of requiring a very large minimum current load, in the order of 100 uA, in order to maintain stability of the LDO voltage regulator.
Yet another example of an LDO voltage regulator is described in R. J. Milliken, J. Silva-Martinez, E. Sanchez-Sinencio, “Full on-chip CMOS low-dropout voltage regulator ”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 54, No. 9, September 2007, Pages: 1879-1890 (hereinafter, “Milliken”). Milliken utilizes a differentiator loop to sense changes in the output voltage of the LDO voltage regulator, and provides a fast negative feedback path for load transients. The differentiator loop also acts as a “Miller capacitor” to stabilize the LDO voltage regulator, by splitting the poles of the circuit. Milliken uses a “cascode” current mirror to guarantee proper current distribution at the gate of the pass transistor. However, a proper current distribution is difficult to maintain at the low power supply voltages and the shrinking device sizes that are common trends in the art. Lack of proper current distribution could result in a large current offset. Moreover, Milliken's technique to control peak gain of the LDO voltage regulator requires a large number of iterations to achieve convergence.
Yet another LDO implementation is seen in Texas Instrument's product, “TPS73601.” The TPS73601 is a standalone implementation of an LDO voltage regulator, which includes a charge pump and a “servo” block to speed up voltage changes at the gate of the pass transistor. The servo block uses a comparator to measure output voltage. When the output voltage is lower than a specified voltage, i.e. if there is an “undershoot,” a sourcing current will be increased. On the other hand, if an overshoot occurs, a sinking current will be increased. Implementation of the TPS73601 requires additional circuitry which consumes a large quiescent current, and consequently is not power efficient.
Accordingly, there exists a need in the art for efficient capacitor-less solutions for LDO voltage regulators, which are not burdened by the drawbacks of above described techniques.